1. Field of the Invention
The present invention relates to a frequency synthesizer, also referred to as controlled oscillator circuit, for use in particular in radio frequency transmitters and receivers. It can be used in the field of mobile telephones in particular, for which fast locking onto a carrier is particularly essential. One object of the invention is therefore to provide means for effective locking on.
2. Description of the Prior Art
In the mobile telephone field, in particular in the GSM (Global System for Mobile communications) and using the TDMA (Time-Division Multiple Access) technique, communication channels are set up to connect mobile telephones to base stations. A channel is defined by a time slot chosen from a plurality of time slots in the same frame. In one of the best known applications a frame comprises eight windows. Another feature of a channel is that it is associated with a carrier frequency. A set of modulation bands is therefore distributed within a range of transmit or receive frequencies. For example, according to the GSM standard a band has a width of 200 kHz and there are more than 100 different carrier frequencies in a range.
Because of propagation deficits at some frequencies between some locations, it is accepted that a frequency law obliges the carrier frequency (at the bandwidth in use) of a particular channel to change periodically. In practice it is changed for every frame. Thus the connection between a mobile telephone and a base station uses a carrier frequency that changes regularly. This requires a transceiver frequency synthesizer that can hop regularly and quickly from one carrier frequency to another.
Under the GSM standard, a time slot has a standardized duration of 577 microseconds. A frame of eight windows therefore has a duration of 4.615 milliseconds. One slot in a frame is used to transmit and another slot in the same frame is used to receive. The time difference between the transmit time slot and the receive time slot is normally at least equal to 1.5 times the duration of a time slot. This means that a mobile telephone transceiver, in particular a transceiver in a mobile telephone, has approximately 865 microseconds to lock onto the carrier frequency allocated to it, in particular to provide duplex communication.
However, in GPRS/HSCSD (General Packet Radio Service/High Speed Circuit Switch Data) systems, in order to increase the data bit rate, a mobile telephone and/or the base station can transmit and/or receive radio signals during successive time slots of the same frame. It is therefore possible for two, three or four successive slots of the some frame to be allocated to one direction of communication between a mobile telephone and a base station. In this case, the carrier frequency does not change from one slot to the other.
However, this kind of practice has led to modification of the standard. Because of such consecutive use, the number of slots remaining available in the same frame is reduced, with the result that it is no longer possible to provide a time separation of at least 1.5 times the slot duration between the two communication directions. This being the case, the standard provides for only one time slot to be neutralized between transmission and reception. As a result, the acquisition times for the oscillators to lock onto the carrier frequencies are reduced. Whereas before, with 865 microseconds available, a lock-on time of 500 microseconds was acceptable, this is no longer acceptable if the acquisition time is reduced to 577 microseconds.
Presetting the frequency of the phase-locked loop (PLL) of the synthesizer to accelerate locking onto a carrier frequency is described in U.S. Pat. No. 4,105,948.
To this end, the PLL is opened for a short time period by a switch between the loop filter and the voltage-controlled oscillator (VCO) and an external voltage is fed to the VCO to force it to generate a signal whose frequency is close to the required frequency. Then, after a particular time-delay, the phase-locked loop is closed again for the synthesizer to adjust itself automatically to the new carrier frequency.
The external voltage applied to the oscillator to force it to change frequency virtually instantaneously is deduced from the nominal gain of the voltage-controlled oscillator. The presetting of the voltage-controlled oscillator of the PLL is more effective when the gain of the VCO is known accurately.
However, it has been found that, after installation, the real gain of the voltage-controlled oscillator can vary as a function of various parameters, for example the external temperature or the time for which the oscillator has been in operation. Consequently, the nominal gain of the VCO and its real gain can be significantly different, depending on external operating parameters, which makes presetting less effective and therefore increases the time for the synthesizer to lock onto the new carrier frequency.
It is therefore clear that it is important to master the variation in the gain of the VCO to minimize the acquisition time of the synthesizer.
Another, related problem of prior art phase-locked loop frequency synthesizers is that of processing noise in the loop.
Prior art synthesizers conventionally include a voltage-controlled oscillator which is controlled by comparing the phase of the signal produced by the oscillator with the phase of a reference signal representative of the required oscillation frequency. This requires the provision in the control loop of a low-pass filter whose bandwidth is limited by the comparison frequency of the phase comparator.
A phase comparator compares signals and produces an error signal at its output. The oscillator is controlled by the error signal. The error signal is smoothed by a low-pass filter. The cut-off frequency of the low-pass filter is substantially equal to one tenth of the comparison frequency. At the frequencies considered here, with a comparison frequency of 200 kHz, this requires a filter with a time constant of the order of 50 microseconds. The acquisition time is then of the order of 500 microseconds, on average, and cannot be reduced.
If a synthesizer of the above kind is used for transmission, the reference frequency is modulated at the input of the phase comparator. A circuit of this kind requires a greater bandwidth of the loop and therefore of the loop filter between the phase comparator and the voltage-controlled oscillator.
Consequently, noise within the bandwidth of the loop is increased and in particular it is difficult to conform to the spectrum recommended by the GSM standard.
An object of the invention is therefore to propose a phase-locked loop frequency synthesizer having improved noise characteristics compared to the prior art. Another object of the invention is to propose a phase-locked loop frequency synthesizer in which the variations in the gain of the voltage-controlled oscillator can be controlled.
A further object of the invention is to propose a phase-locked loop frequency synthesizer having a short acquisition time.
To this end, the invention provides a frequency synthesizer including a phase regulation loop including a voltage-controlled oscillator, a reference oscillator, a phase-locked loop receiving as input the signal from the voltage-controlled oscillator and the signal from the reference oscillator, delivering at its output the control voltage for the voltage-controlled oscillator and including a phase comparator connected directly to an output of the reference oscillator and to an output of the voltage-controlled oscillator via a feedback loop including a counter-divider, means for feeding a modulation signal between the phase comparator and the voltage-controlled oscillator and modulation compensation means for preparing a compensation signal from the modulation signal and for feeding the compensation signal into the feedback loop upstream of the counter-divider to cancel the modulation of the signal at the output of the voltage-controlled oscillator applied to the input of the counter.
In one embodiment the synthesizer according to the invention includes means for determining the real gain of the voltage-controlled oscillator from at least one measurement parameter and the determination means are adapted to deliver a signal representative of the real gain of the voltage-controlled oscillator.
In one embodiment the synthesizer according to the invention further includes divider means having a first input adapted to receive from the determination means the signal representative of the real gain of the voltage-controlled oscillator, a second input adapted to receive the modulation signal, and an output delivering the modulation signal divided by the real gain of the voltage-controlled oscillator and connected to an input of a summation circuit between the voltage-controlled oscillator and a loop filter between the output of the phase comparator and the input of the voltage-controlled oscillator.
The synthesizer according to the invention can have any one or more of the following features:
the synthesizer further includes a loop filter between the output of the phase comparator and the input of the voltage-controlled oscillator and the determination means include measuring means for measuring the output voltage of the loop filter at a first frequency and at a second frequency and a calculation unit for calculating the real gain of the voltage-controlled oscillator by dividing the difference between the first and second frequencies by the difference between the first and second control voltages respectively measured at the first and second frequencies,
the determination means further include an analog-to-digital converter adapted to convert a voltage measured by the measuring means into a digital signal and the calculation unit is a digital unit,
the determination means include a temperature sensor, a memory for storing a table of the gain of the voltage-controlled oscillator as a function of temperature and a control unit for delivering the real gain of the voltage-controlled oscillator as a function of the measured temperature and the gain values stored in the memory,
the determination means include means for measuring the operation time of the voltage-controlled oscillator, a memory for storing a table of the gain of the voltage-controlled oscillator as a function of its operating time and a control unit for delivering the real gain of the voltage-controlled oscillator as a function of the operation time delivered by the counter and the gain values stored in the memory,
the compensation means include a multiplier for multiplying the modulation signal by 2xcfx80, an accumulator whose input is connected to the output of the multiplier, a unit for forming an in-phase signal I and a quadrature signal Q, a first mixer, and a second mixer, wherein each mixer is in a branch of the feedback loop upstream of the counter-divider, the first mixer is adapted to mix the in-phase signal I with the output signal of the voltage-controlled oscillator and the second mixer is adapted to mix the quadrature signal Q with the output signal of the voltage-controlled oscillator phase-shifted by xcfx80/2.
Other features and advantages of the invention emerge from the following description, which is given by way of non-limiting example and with reference to the accompanying drawings.